MLRISC

MLRISC Contributors Requirements How to Obtain MLRISC

Overview

Problem Statement Contributions MLRISC Based Compiler MLRISC Intermediate Representation MLRisc Generation Back End Optimizations Register Allocation Machine Description Garbage Collection Safety System Integration Optimizations Graphical Interface Line Counts Systems Using MLRISC Future Work

System

Architecture of MLRISC The MLTREE Language MLTree Extensions MLTree Utilities Instruction Selection Assemblers Machine Code Emitters Delay Slot Filling Span Dependency Resolution The Graph Library The Graph Visualization Library Basic Compiler Graphs The MLRISC IR SSA Optimizations ILP Optimizations Optimizations for VLIW/EPIC Architectur... Register Allocator

Back Ends

The Alpha Back End The PA RISC Back End The Sparc Back End The Intel x86 Back End The PowerPC Back End The MIPS Back End The TI C6x Back End

Basic Types

Annotations Cells Cluster Client Defined Constants Client Defined Pseudo Ops Instructions Instruction Streams Label Expressions Labels Regions Regmap

# The Sparc Back End

The Sparc Back End

General Setup for V8 General Setup for V9 Specializing the Sparc Back End

The Sparc back end can function in two different modes:

Sparc V8
  This is V8 instruction set is used. In this mode the processor behaves like a 32-bit processor. In this mode we assume we have 16 floating point registers numbered `%f0, %f2, %f4, ..., %f30`. These are all in IEEE double precision.
Sparc V9
  This generates code assuming the V9 instruction set is used. In this mode the processor functions at 64-bit. In this mode the floating point processors can number from `%f0, %f2, %f4, ..., %f62`. These are all in IEEE double precision.

  New V9 instructions include the 64-bit extended version of multiplications, divisions, shifts, and load and store.

           MULX SMULX DIVX SLLX SRLX SRAX LDX STX

  Also, V9 includes conditional moves and more general form of branches.
  MOVcc
    conditional moves on condition code
  FMOVcc
    conditional moves on condition code
  MOVR
    conditional moves on integer condition
  BR
    branch on integer register with prediction
  BP
    branch on integer condition with prediction

## General Setup for V8

The SPARC architecture has 32 general purpose registers (`%g0` is always 0) and 32 single precision floating point registers.

Some Ugliness: double precision floating point registers are register pairs. There are no double precision moves, negation and absolute values. These require two single precision operations. I've created composite instructions `FMOVd`, `FNEGd` and `FABSd` to stand for these.

All integer arithmetic instructions can optionally set the condition code register. We use this to simplify certain comparisons with zero in the instruction selection process.

Integer multiplication, division and conversion from integer to floating go thru the pseudo instruction interface, since older sparcs do not implement these instructions in hardware.

In addition, the trap instruction for detecting overflow is a parameter. This allows different trap vectors to be used.

## General Setup for V9

## Specializing the Sparc Back End

Lal George
Allen Leung

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Last modified: Fri Oct 11 18:19:52 UTC 2019 by buildd@x86-grnet-02