MLRISC

MLRISC Contributors Requirements How to Obtain MLRISC

Overview

Problem Statement Contributions MLRISC Based Compiler MLRISC Intermediate Representation MLRisc Generation Back End Optimizations Register Allocation Machine Description Garbage Collection Safety System Integration Optimizations Graphical Interface Line Counts Systems Using MLRISC Future Work

System

Architecture of MLRISC The MLTREE Language MLTree Extensions MLTree Utilities Instruction Selection Assemblers Machine Code Emitters Delay Slot Filling Span Dependency Resolution The Graph Library The Graph Visualization Library Basic Compiler Graphs The MLRISC IR SSA Optimizations ILP Optimizations Optimizations for VLIW/EPIC Architectur... Register Allocator

Back Ends

The Alpha Back End The PA RISC Back End The Sparc Back End The Intel x86 Back End The PowerPC Back End The MIPS Back End The TI C6x Back End

Basic Types

Annotations Cells Cluster Client Defined Constants Client Defined Pseudo Ops Instructions Instruction Streams Label Expressions Labels Regions Regmap

# Architecture of MLRISC

Architecture of MLRISC

Core Components Optimization Modules Basic Concepts How Things Are Fit Together

## Core Components

The core components of MLRISC allow the client to quickly construct an backend for various architectures. These components include:

- The MLTREE language, which is a RTL-like intermediate language that is used by the client to communicate to the MLRISC system. A client is responsible for writing the module that generates MLTREE from the source program representation.
- Instruction selection modules, which generates target machine instructions from MLTREE.
- The Register Allocator, which performs register allocation.
- Assemblers, which emits assembly code.

For systems that require direct machine code generation, the following modules are included:

- Span dependency resolution modules, which compute addresses from symbolic addresses, fill delay slots, and expand instructions that are span dependent
- Machine code emitters, which emit executable machine code into a binary stream.

## Optimization Modules

In addition, MLRISC has been enhanced to support various types of machine level optimizations. These include:

- Core optimizations, which includes various types of control flow transformation, and architectural specific peephole optimizations.
- SSA based scalar optimizations
- ILP optimizations for superscalars
- ILP optimizations for VLIW/EPIC architectures
- GC safety analysis

## Basic Concepts

Basic concepts in MLRISC are:

- Instructions -- the instruction set of the target architecture.
- Cells -- which describes registers, memory and other mutable resources in the machine.
- Regions -- a client defined abstract type used to represent aliasing information available from the front-end.
- Constants -- a client defined place holder used to represent constants whose values are unknown in the front-end.
- Pseudo Ops -- a client defined

- Annotations -- this is a generic mechinism for propagating information in the MLRISC sstem. The client may attach arbitrary annotation of various granularity to MLRISC's program representation, which can then be propagated to later phases. These can be information related to profiling frequency, dependence, comments, and/or types. The same mechanism is also used to propagate analysis information one optimization phase to another.
- Instruction Streams -- an abstraction for describing a stream of instructions. Instruction streams are used to connect modules such as instruction selection, assembler, machine code emitter, and control flow graph builder.
- Regmap -- a mapping between registers names. MLRISC register allocators represent the result of register allocation as a regmap.
- Labels -- a type representing symbolic labels.
- Label Expressions -- a type representing constant expressions involving symbolic labels.

## How Things Are Fit Together

MLRISC uses two different program representations, clusters and MLRISC IR.

- Cluster is light-weight representation that is used when only the most basic optimizations are required.
- MLRISC IR is more heavy-weight representation that is built from the MLRISC graph library and the MLRISC compiler graph library. MLRISC IR allows more complex transformations and analysis of the program graph.

Conversion modules between the two representations are provided.

In general MLRISC optimization phases are transformations applied on one of these representations. Optimizations may be chained together to form a compiler backend. For example, a minimal backend consists of

- the instruction selection module, which translates MLTree into target instructions,
- the flowgraph builder, which conversts a stream of target instructions into a cluster,
- the register allocator, which performs register allocation, and
- the assembly code emitter, which generates assembly output

Lal George
Allen Leung

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Last modified: Mon Oct 3 20:52:35 UTC 2022 by buildd@x86-grnet-02