MLRISC

MLRISC Contributors Requirements How to Obtain MLRISC

Overview

Problem Statement Contributions MLRISC Based Compiler MLRISC Intermediate Representation MLRisc Generation Back End Optimizations Register Allocation Machine Description Garbage Collection Safety System Integration Optimizations Graphical Interface Line Counts Systems Using MLRISC Future Work

System

Architecture of MLRISC The MLTREE Language MLTree Extensions MLTree Utilities Instruction Selection Assemblers Machine Code Emitters Delay Slot Filling Span Dependency Resolution The Graph Library The Graph Visualization Library Basic Compiler Graphs The MLRISC IR SSA Optimizations ILP Optimizations Optimizations for VLIW/EPIC Architectur... Register Allocator

Back Ends

The Alpha Back End The PA RISC Back End The Sparc Back End The Intel x86 Back End The PowerPC Back End The MIPS Back End The TI C6x Back End

Basic Types

Annotations Cells Cluster Client Defined Constants Client Defined Pseudo Ops Instructions Instruction Streams Label Expressions Labels Regions Regmap

# Back End Optimizations

Once MLRisc trees have been generated, they are passed into a module that generates a flowgraph of target machine instructions. Again, this module and all subsequent optimization phases have been specialized to the front end. Nearly all instruction selection modules provided by MLRISC use a simple tree pattern matching algorithm rather than the more heavy weight BURG tools --- including the x86 It is important to emphasis that all optimizations are performed on the flowgraph of target machine instructions and not MLRisc immediate IR. There is complete flexibility in the order, and nature of the optimizations performed.

Lal George
Allen Leung

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Last modified: Mon Oct 3 20:52:35 UTC 2022 by buildd@x86-grnet-02